Abstract: Heterogeneous integration enabled by 3D technology is one of the innovations for future microprocessor design. The heterogeneous integration of DRAM and multi-core processor in the 3D architecture offer much higher memory bandwidth, and mitigating the memory wall problem in off-chip DRAM design. However, stacking of multiple memory tiers comes out a serious thermal problem. In this paper, we propose a segment-based task scheduling methodology for this stacked memory architecture, and resolve this problem by ILP formulations. The proposed approach is integrated with task allocation and memory mapping in our system. Experimental results from the thermal simulation tool show that the proposed segmentbased approach can reduce the thermal temperature by about 10% than using the task scheduling approach directly. REFERENCES [1] N. Madan and R. Balasubramonian, “Leveraging 3D Technology for Improved Reliability”, 40th International Symposium on Microarchitecture, 2007. [2] K. Puttaswamy and G. H. Loh, “Thermal Herding: Microarchitecture Techniques for Controlling HotSpots in High-Performance 3DIntegrated Processors”, 13th International Symposium on High Performance Computer Architecture, 2007. [3] Changyun Zhu, Zhenyu Gu, Li Shang, R.P. Dick and R. Joseph, “Three-Dimensional ChipMultiprocessor Run-Time Thermal Management”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.8, pp. 1479-1492, August 2008. [4] Han Wang, Yuzhuo Fu, Ting Liu and Jiafang Wang, “Thermal management via task scheduling for 3D NoC based multi-processor”, International SoC Design Conference (ISOCC), pp.440-444, November 2010. [5] Xiuyi Zhou, Jun Yang, Yi Xu, Youtao Zhang and Jianhua Zhao, “Thermal-Aware Task Scheduling for 3D Multicore Processors”, IEEE Transactions on Parallel and Distributed Systems, vol. 21, no. 1, pp. 60-71, January 2010. [6] Jiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen and Yongxin Zhu, “Real-Time C. Wei-Kai et al. International Journal of Circuits and Electronics http://www.iaras.org/iaras/journals/ijce
Keywords: 3D architecture, TSVs, memory mapping, task scheduling
Cite this paper
Wei-Kai Cheng, Ting-Wei Hsu, Ruey-Yeu Wang. (2016) Segment-Based Task Scheduling for Thermal Optimization of Stacked Memory Architecture. International Journal of Circuits and Electronics, 1 , 39-48

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