Wei-Kai Cheng, Ting-Wei Hsu, Ruey-Yeu Wang



Segment-Based Task Scheduling for Thermal Optimization of Stacked Memory Architecture

pdf PDF


3D architecture, TSVs, memory mapping, task scheduling


Heterogeneous integration enabled by 3D technology is one of the innovations for future microprocessor design. The heterogeneous integration of DRAM and multi-core processor in the 3D architecture offer much higher memory bandwidth, and mitigating the memory wall problem in off-chip DRAM design. However, stacking of multiple memory tiers comes out a serious thermal problem. In this paper, we propose a segment-based task scheduling methodology for this stacked memory architecture, and resolve this problem by ILP formulations. The proposed approach is integrated with task allocation and memory mapping in our system. Experimental results from the thermal simulation tool show that the proposed segmentbased approach can reduce the thermal temperature by about 10% than using the task scheduling approach directly.


[1] N. Madan and R. Balasubramonian, “Leveraging 3D Technology for Improved Reliability”, 40th International Symposium on Microarchitecture, 2007.

[2] K. Puttaswamy and G. H. Loh, “Thermal Herding: Microarchitecture Techniques for Controlling HotSpots in High-Performance 3DIntegrated Processors”, 13th International Symposium on High Performance Computer Architecture, 2007.

[3] Changyun Zhu, Zhenyu Gu, Li Shang, R.P. Dick and R. Joseph, “Three-Dimensional ChipMultiprocessor Run-Time Thermal Management”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.8, pp. 1479-1492, August 2008.

[4] Han Wang, Yuzhuo Fu, Ting Liu and Jiafang Wang, “Thermal management via task scheduling for 3D NoC based multi-processor”, International SoC Design Conference (ISOCC), pp.440-444, November 2010.

[5] Xiuyi Zhou, Jun Yang, Yi Xu, Youtao Zhang and Jianhua Zhao, “Thermal-Aware Task Scheduling for 3D Multicore Processors”, IEEE Transactions on Parallel and Distributed Systems, vol. 21, no. 1, pp. 60-71, January 2010.

[6] Jiayin Li, Meikang Qiu, Jianwei Niu, Tianzhou Chen and Yongxin Zhu, “Real-Time C. Wei-Kai et al. International Journal of Circuits and Electronics http://www.iaras.org/iaras/journals/ijce ISSN: 2367-8879 47 Volume 1, 2016 Constrained Task Scheduling in 3D Chip Multiprocessor to Reduce Peak Temperature”, 8th International Conference on Embedded and Ubiquitous Computing (EUC), pp. 170-176, December 2010.

[7] G. L. Loi, B. Agarwal, N. Srivastava, S.-C. Lin, and T. Sherwood, “A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy”, 43rd Design Automation Conerence (DAC), 2006.

[8] C. C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari, “Bridging the Processor-Memory Performance Gap with 3D IC Technology”, IEEE Design and Test of Computers, 22(6): pp. 556–564, Nov.-Dec. 2005.

[9] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, and D. Pantuso, “Die stacking (3D) microarchitecture”, 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469–479, 2006.

[10] K. L. Tai, “System-In-Package (SIP): Challenges and Opportunities”, Asia and South Pacific Design Automation Conference (ASPDAC), pp. 191-196, 2000.

[11] Y. Xie, G. Loh, B. Black, and K. Bernstein, “Design space exploration for 3D architectures”, ACM Journal of Emerging Technologies in Computing Systems, 2006.

[12] Y. I. Kim, K. H. Yang and W. S. Lee, “Thermal Degradation of DRAM Retention Time: Characterization and improving techniques”, 42nd IEEE International Reliability Physics Symposium, pp. 667-668, April 2004.

[13] Ang-Chih Hsieh and TingTing Hwang, “Thermal-aware memory mapping in 3D designs”, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1361- 1366, April 2009.

[14] Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai and Shih-Chieh Chang, “Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization”, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, March 2011.

[15] G. H. Loh, “3d-stacked memory architectures for multicore processors”, International Symposium on Computer Architecture (ISCA), pp. 453-464, 2008.

[16] Y. Xie, “Processor Architecture Design Using 3D Integration Technology”, 23rd International Conference on VLSI Design, pp. 446-451, January 2010.

[17] Q. Zou, Y. Chen and Y. Xie, A. Su, “System-level design space exploration for three-dimensional (3D) SoCs”, 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 385- 388, October 2011.

[18] http://www.spec.org/

[19] D. C. Burger, T. M. Austin and S. Bennett, “Evaluating Future Microprocessors– The SimpleScalar Tool Set”, Technical Report 1342,University of Wisconsin-Madison, CS Department, June 1997.

[20] W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan. “Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2009.

[21] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge and R. B. Brown, “MiBench: A free, commercially representative embedded benchmark suite”, Proceedings of the Workload Characterization, 2001. [22] M. K. Gowan et al., “Power Considerations in the Design of the Alpha 21264 Microprocesso”r, Design Automation Conerence (DAC), pp. 726-731, 1998. [23] http://www.micron.com

Cite this paper

Wei-Kai Cheng, Ting-Wei Hsu, Ruey-Yeu Wang. (2016) Segment-Based Task Scheduling for Thermal Optimization of Stacked Memory Architecture. International Journal of Circuits and Electronics, 1, 39-48


Copyright © 2017 Author(s) retain the copyright of this article.
This article is published under the terms of the Creative Commons Attribution License 4.0