3D architecture, TSVs, memory mapping, task scheduling
Heterogeneous integration enabled by 3D technology is one of the innovations for future microprocessor design. The heterogeneous integration of DRAM and multi-core processor in the 3D architecture offer much higher memory bandwidth, and mitigating the memory wall problem in off-chip DRAM design. However, stacking of multiple memory tiers comes out a serious thermal problem. In this paper, we propose a segment-based task scheduling methodology for this stacked memory architecture, and resolve this problem by ILP formulations. The proposed approach is integrated with task allocation and memory mapping in our system. Experimental results from the thermal simulation tool show that the proposed segmentbased approach can reduce the thermal temperature by about 10% than using the task scheduling approach directly.
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Cite this paper
Wei-Kai Cheng, Ting-Wei Hsu, Ruey-Yeu Wang. (2016) Segment-Based Task Scheduling for Thermal Optimization of Stacked Memory Architecture. International Journal of Circuits and Electronics, 1, 39-48