Design of High-speed Dynamic Packet Filtering Firewall for IPv6 based on FPGA

Abstract: Network security issues are becoming increasingly acute. A computer network exposed to the Internet without any security protection is at great risk. This paper proposes the packet filtering firewalls system based on FPGA. This system connects the high-speed firewall filtering module and the CPU (OR1200). The Internet Protocol Version 6 (IPv6) network data package is sent to test successfully by the PC client. Experimental results show that the system process the whole IPv6 data packet with 920ns and the complete design uses a small portion of the Altera StratixII/ EP2S60F672C5 FPGA, 25% of the logic blocks and 11% of the memory blocks. So the system not only has ideal functionality but greatly improves the data transmission speed