In this paper, we present the customization methodology of high speed Flash ADC by optimizing its various components through CMOS channel length i.e comparator, so that the overall performance of the resulting Flash ADC or CMOS made device(s) is improved over traditional Flash ADC’s. Together with high speed as a parameter, components are designed so that they operate with sampling frequency as high as 70-75 MHz with lowest power consumption and operate on power supply voltage down to 2V for compatible with low power digital portion of the design as well as occupy less chip area. All the components are designed using the 90 nm CMOS technology.
. Koen Uyttenove and Michiel S.J.Steyaert,”A1.8V 6-Bit 1.3 GHz Flash ADC in 0.25μm CMOS “, IEEE J. Solid-State Circuits,Vol -38,NO-7,July 2003,pp.1115-1122.
. Robert C..Taft and Maria Rosaria Tursi,”A 100- MS/s 8b CMOS Subranging ADC with Sustained Parametric Performance from 3.8V Down to 2.2V”, IEEE J. Solid-State Circuits, Vol -36, NO-3, March 2001,pp.330-338.
. Bram Nauta and Ardie G.W.Venes,”A 70MS/s 110- m W 8-b CMOS Folding and Interpolating A/D Converter”, IEEE J. Solid-State Circuits, Vol-.30, NO.-12,Dec 1995 ,pp.1302-1308.
. Behzad Razavi and Bruce A.Wooley,”A12-b 5- MS/s Two Step CMOS A/D Converter”, IEEE J. Solid-State Circuits, Vol -27, NO-12,Dec 1992,pp.1667-1678.
. G.M Yin,F.Opt Eynde and W.Sansen,”A high Speed CMOS Comparator with 8-b Resolution”, IEEE J. Solid-State Circuits, Vol- 27, NO-2,Feb 1992,pp.208-211.
. Francesco Brianti,Alessandro Manstretta,Guido Torelli,” High Speed Autozeroed CMOS Comparator for multistep A/D Conversion”, Microelectronics J., Vol- 29 ,1998 pp.845-853
. Hendrik van der Plog and Robert Remmers,”A 3.3V,10-b,25M samples/s Two-Step ADC in 0.35-μm CMOS”, IEEE J. Solid-State Circuits, Vol- 34, NO- 12,Dec 1999,pp.1803-1811.
. Donald A. Kerth,Navdeep S. Sooch and Eric J. Swanson,”A 12-bit 1-MHz Two-Step Flash ADC ”, IEEE J. Solid-State Circuits, Vol- 24, NO-2,April 1989,pp.250-255.
. Mikael GustavssonJ. Jacob Wikner and Nianxiong Nick Tan,” CMOS Data Converters for Communications”, Kluwer Acadamic Publishers, 2000.
. Thomas B. Cho,David W. Cline,Cormac S.G.Conroy and Paul R. Gray”Design Considerations for High-Speed Low-Power Low-Voltage CMOS
Cite this paper
Umesh Kumar, Ashish Mishra. (2017) CMOS Customization of Comparator. International Journal of Circuits and Electronics, 2, 99-102
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